Semiconductor devices continue to decrease in size and increase in power-density, resulting in a number of challenges for system designers. One of the primary challenges relates to microelectronic device cooling—i.e., how to efficiently remove heat generated by the device during operation.
Traditional multi-layer high-density interconnects (HDI) typically have an organic substrate and are soldered to a printed circuit board (PCB) such that the heat-generating chips have an efficient heat transfer path to the board. In advanced multi-layer embedded chip packages, however, it is possible to incorporate one or more semiconductor devices (e.g., memory devices) within or on top of one or more build-up layers containing vias, dielectrics, etc., which are held together in an integrated package by encapsulants and the like. Because of the thermal boundary conditions presented by such interconnect structures, it is difficult to attach power amplifiers and other high-power components in such a way that heat from these power devices can be dissipated efficiently. That is, as such multi-layer embedded chip packages consist of low thermal conductivity layers of dielectric with sparsely-distributed metal interconnects and electrical vias, their effective thermal resistance is very high. It is therefore undesirable to stack high-power amplifiers, microprocessors, and other components on these multi-layer structures.
Accordingly, there is a need for methods and structures that improve heat transfer in embedded chip packages by overcoming these and other shortcomings of the prior art. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.